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AC '97 SoundMAX(R) Codec AD1888
FEATURES
AC '97 2.3 compatible features 6 DAC channels for 5.1 surround 90 dB dynamic range 20-bit PCM DACs S/PDIF output Integrated stereo headphone amplifiers Phone, aux, and line-in High quality CD input Selectable MIC input Mono output External amplifier power-down control Double rate audio (fS = 96 kHz) Power-management modes 48-lead LQFP and 48-lead LFCSP
ENHANCED FEATURES
Selectable front and rear MIC inputs with preamp Integrated PLL for system clocking Crystal-free operation Variable sample rate 7 kHz to 96 kHz Jack sense (auto topology switching) Software-controlled VREF_OUT for MIC bias Software enabled outputs for jack sharing Auto down-mix and channel spreading modes
FUNCTIONAL BLOCK DIAGRAM
MIC1 MIC2 PHONE_IN CD_L CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R G M PLL DIFF AMP G M 16-BIT - ADC 16-BIT - ADC
AD1888
G
XTAL_IN
XTAL_OUT
ADC SLOT LOGIC
ID0
ID1
GA GA MONO_OUT M A M GA M GA M M GA M
GA M GA GA M M GA M
AC '97 CONTROL REGISTERS
AC '97 INTERFACE
RESET
SYNC
BIT_CLK
SDATA_OUT DAC SLOT LOGIC 20-BIT - DAC 20-BIT - DAC SPDIF TX SPDIF_OUT
SDATA_IN
LINE_OUT_L
MZ
A M GA
LINE_OUT_R
MZ
A M GA
M CENTER_OUT MZ A
M
M
M
M
M M GA 20-BIT - DAC 20-BIT - DAC
EAPD
EAPD
LFE_OUT
MZ
A M G = GAIN A = ATTENUATION M = MUTE Z = HIGH-Z M GA GA
JACK SENSE LOGIC VOLTAGE REFERENCE
JS0 JS1
VREF VREFOUT
04294-001
SURR_L/ HP_OUT_L SURR_R/ HP_OUT_R
HP
M
A
20-BIT - DAC 20-BIT - DAC
HP
M
A M GA
Figure 1.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005 Analog Devices, Inc. All rights reserved.
AD1888 TABLE OF CONTENTS
Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Timing Parameters ........................................................................... 6 Absolute Maximum Ratings............................................................ 8 Environmental Conditions.......................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions..............................9 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
8/05--Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 31 Changes to Ordering Guide .......................................................... 31 10/03--Revision 0: Initial Version
Rev. A | Page 2 of 32
AD1888 SPECIFICATIONS
TEST CONDITIONS
Standard Test Conditions
Unless otherwise noted: * Temperature * Digital Supply (DVDD) * Analog Supply (AVDD) * Sample Rate (fS) * Input Signal * Analog Output Pass Band 25C 3.3 V 5.0 V 48 kHz 1 kHz 20 Hz to 20 kHz
DAC Test Conditions
* * * * * * * * Calibrated -3 dB attenuation relative to full scale 0 dB input 10 k output load LINE_OUT, MONO_OUT, CENTER_OUT, and LFE_OUT 32 output load (HP_OUT) Calibrated 0 dB gain Input -3.0 dB relative to full scale Min Typ Max Unit
ADC Test Conditions
Table 1.
Parameter ANALOG INPUT Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, CD, AUX, PHONE_IN MIC_IN with 30 dB Preamp MIC_IN with 20 dB Preamp MIC_IN with 10 dB Preamp MIC_IN with 0 dB Gain Input Impedance 1 Input Capacitance1 MASTER VOLUME Step Size (Line Out, Mono Out, Surround Out, Center, LFE) Output Attenuation Range Span1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range Span ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT LINE, AUX, or PHONE to LINE_OUT1 MIC1 or MIC2 (Note: MIC Gain of 0 dB) to LINE_OUT1 Step Size All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs DIGITAL DECIMATION AND INTERPOLATION FILTERS1 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
1 2.83 0.032 0.089 0.1 0.283 0.316 0.894 1 2.83 20 5 1.5 46.5
7.5
V rms V p-p V rms V p-p V rms V p-p V rms V p-p V rms V p-p K pF dB dB dB dB dB
80 1.5 22.5
90 90 90 1.5 46.5 0 0.4 x fS 0.6 x fS -74 16/fS 0 0.4 x fS 0.09 0.6 x fS
dB dB dB dB dB Hz dB Hz Hz dB sec s
Rev. A | Page 3 of 32
AD1888
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) AVDD = 5.0 V Dynamic Range (-60 dB Input THD + N Referenced to FS, A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion1 (CCIF Method) ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 (0 dB Gain, HPF On) DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD), LINE_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), HP_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), CENTER/LFE, AVDD = 5.0 V Dynamic Range (-60 dB Input THD + N Referenced to FS A-Weighted) AVDD = 5.0 V, All Outputs Signal-to-Intermodulation Distortion1 (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Read LINE_OUT_R; Input R, Zero L, Read LINE_OUT_L, 10 k Load)1 Total Audible Out-of-Band Energy1 (Measured from 0.6 x fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT/MONO_OUT, CENTER_OUT, LFE_OUT Output Impedance1 External Load Impedance1 (LINE_OUT, CENTER_OUT/LFE_OUT, MONO_OUT) Output Capacitance1 External Load Capacitance1 Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance1; HP_OUT VREF VREF_OUT (VREFH = 0) VREF_OUT (VREFH = 1) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current Min Typ 16 -78 80 84 -85 -85 10 0.5 10 20 -80 -70 -80 90 88 10 0.7 -80 -40 1 2.83 300 10 15 100 1 32 2.05 2.25 2.25 3.65 5 0.65 x DVDD 0.35 x DVDD 0.9 x DVDD -10 -10 0.1 x DVDD +10 +10 2.45 Max Unit Bits dB dB dB dB dB % dB mV Bits dB dB dB dB dB % dB dB dB V rms V p-p k pF pF V rms V V V mA mV V V V V A A
5
Rev. A | Page 4 of 32
AD1888
Parameter POWER SUPPLY Power Supply Range, Analog (AVDD) Power Supply Range, Digital (DVDD) Power Dissipation 5 V/3.3 V Analog Supply Current 5 V (AVDD) Digital Supply Current 3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
1
Min 4.75 3.15
Typ
Max 5.25 3.45
Unit V V mW mA mA dB
563 70 53 -40
Guaranteed but not tested.
Parameter POWER-DOWN STATES 2 Fully Active ADC FRONT DAC SURROUND DAC CENTER/LFE DAC ADC + ALL DACs Mixer ADC + Mixer ALL DACs + Mixer ADC + ALL DACs + Mixer Standby Headphone Standby
1 2
PR[K:I] 1 000 000 000 010 101 111 000 000 111 111 111 000
PR[6:0]1 000 0000 000 0001 000 0010 000 0000 000 0000 000 0011 000 0100 000 0101 000 0110 000 0111 011 1111 100 0000
DVDD Typ 53 44 46 46 46 12 52 45 31 12 0 52
AVDD Typ 70 66 61 61 61 33 44 39 14 8 0 65
Unit mA mA mA mA mA mA mA mA mA mA mA mA
PR bits are controlled in Reg. 2Ah and 26h. Values presented with VREFOUT loaded.
Parameter CLOCK SPECIFICATIONS 1 Input Clock Frequency (XTAL Mode or Clock Oscillator) Input Clock Frequency (Reference Clock Mode) Input Clock Frequency (USB Clock Mode) Recommended Clock Duty Cycle
1
Min
Typ 24.576 14.31818 48.000 50
Max
Unit MHz MHz MHz %
40
60
Guaranteed but not tested.
Rev. A | Page 5 of 32
AD1888 TIMING PARAMETERS
Guaranteed over operating temperature range. Table 2.
Parameter RESET Active Low Pulse Width RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulse Width SYNC Low Pulse Width SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter 1, 2 BIT_CLK High Pulse Width BIT_CLK Low Pulse Width SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to RESET Inactive (SYNC, SDATA_OUT) Rising Edge of RESET to Hi-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from BIT_CLK Rising
1 2
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK
Min 162.8
Typ 1.0 1.3 19.5
Max 400,000
162.8 12.288 1.0
tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF 40 39.7
81.4 750 41.7 41.4 48.0 20.8 4 3 2 2 2 2 2 2 2 2 0 15
4 4 4 4 4 4 4 4
6 6 6 6 6 6 6 6 1.0 25 15 50 15
Unit s ns s s ns MHz ppm ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns
Guaranteed but not tested. Output jitter directly dependent on crystal input jitter.
tRST2CLK tRST_LOW
RESET
tTRI2ACTV
BIT_CLK
tTRI2ACTV
SDATA_IN
Figure 2. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
tSYNC_HIGH
SYNC
04294-003
tSYNC2CLK
BIT_CLK
Figure 3. Warm Reset Timing
Rev. A | Page 6 of 32
04294-002
AD1888
tCLK_LOW
BIT_CLK
tCO
tCLK_HIGH tCLK_PERIOD
BIT_CLK VIH
tSETUP
VIL
tSYNC_LOW
SDATA_OUT
SYNC
04294-004
SDATA_IN SYNC
VOH VOL
04294-007
tSYNC_HIGH tSYNC_PERIOD
tHOLD
Figure 4. Clock Timing
Figure 7. AC-Link Low Power Mode Timing
BIT_CLK
tRISECLK
tFALLCLK
SYNC
RESET
tRISESYNC
tFALLSYNC
SDATA_OUT
SDATA_IN
tSETUP2RST
tRISEDIN tFALLDIN
04294-008
SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O
Hi-Z
tOFF
SDATA_OUT
tRISEDOUT
tFALLDOUT
Figure 5. Signal Rise and Fall Times
04294-005
Figure 8. ATE Test Mode
SLOT 1 SYNC
SLOT 2
BIT_CLK
SDATA_OUT
WRITE TO 0x26
DATA PR4
tS2_PDOWN
04294-006
SDATA_IN BIT_CLK NOT TO SCALE
Figure 6. AC-Link low Power Mode Timing
Rev. A | Page 7 of 32
AD1888 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Power Supplies Digital (DVDD) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min -0.3 -0.3 -0.3 -0.3 0 -65 Max +3.6 +6.0 10.0 AVDD + 0.3 DVDD + 0.3 +70 +150 Unit V V mA V V C C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ENVIRONMENTAL CONDITIONS
Ambient temperature rating: 1 TCASE = Case temperature in C PD = Power dissipation in W JA = Thermal resistance (junction-to-ambient) JC = Thermal resistance (junction-to-case)
1
All measurements per EIA/JESD51 with 2S2P test board per EIA/JESD51-7.
Table 4.
Package LQFP LFCSP JA 50.1C/W 50C/W JC 17.8C/W 25.88C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 8 of 32
AD1888 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SURR_OUT_R/HP_OUT_R SURR_OUT_L/HP_OUT_L
48 47 46 45 44 43 42
41 40 39 38 37 36 LINE_OUT_R (FRONT_R)
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12
13 14 15 16 17 18 19 20 21 22 23 24 PIN 1
MONO_OUT
35 LINE_OUT_L (FRONT_L) 34 AVDD4 33 AVSS4 32 LFE_OUT 31 CENTER_OUT 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1
AVDD3
AD1888
TOP VIEW (Not to Scale)
AUX_L
CD_L
LINE_IN_L
MIC1
MIC2
JS1
JS0
CD_GND_REF
LINE_IN_R
PHONE_IN
AUX_R
CD_R
NC = NO CONNECT
AVDD2
AVSS3
AVSS2
SPDIF
EAPD
ID1
ID0
NC
Figure 9. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic DIGITAL INPUT/OUTPUT 2 XTL_IN 3 XTL_OUT 5 SDATA_OUT 6 BIT_CLK 8 SDATA_IN 10 SYNC 11 RESET 48 SPDIF CHIP SELECTS/CLOCK STRAPPING 45 ID0 46 ID1 JACK SENSE AND EAPD 47 EAPD 17 JS0 16 JS1 ANALOG INPUT/OUTPUT 13 PHONE_IN 14 AUX_L 15 AUX_R 18 CD_L 19 CD_GND_REF 20 CD_ R 21 MIC1 22 MIC2 I/O I O I O/I O I I O I I O I I I I I I I I I I Function Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz, or 48000 MHz). Crystal Output. AC-Link Serial Data Output. AD1888 input stream. AC-Link Bit Clock. 12.288 MHz serial data clock. (Input pin for Secondary mode only.) AC-Link Serial Data Input. AD1888 output stream. AC-Link Frame Sync. AC-Link Reset. AD1888 master H/W reset. SPDIF Output. Chip Select Input 0 (Active Low). Chip Select Input 1 (Active Low). EAPD Output. Jack Sense 0 Input. Jack Sense 1 Input. Monaural Line-Level Input. Auxiliary Input, Left Channel. Auxiliary Input, Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Rear Panel MIC Input. Front Panel MIC Input.
Rev. A | Page 9 of 32
04294-009
AD1888
Pin No. Mnemonic 23 LINE_IN_L 24 LINE_IN_R 31 CENTER_OUT 32 LFE_OUT 35 LINE_OUT_L 36 LINE_OUT_R 37 MONO_OUT 39 SURR_OUT_L/HP_OUT_L 41 SURR_OUT_R/HP_OUT_R FILTER/REFERENCE 27 VREF 28 VREFOUT 29 AFILT1 30 AFILT2 POWER AND GROUND SIGNALS 1 DVDD1 4 DVSS1 7 DVSS2 9 DVDD2 25 AVDD1 26 AVSS1 33 AVSS4 34 AVDD4 38 AVDD2 40 AVSS2 43 AVDD3 44 AVSS3 NO CONNECTS 12 NC 42 NC I/O I I O O O O O O O O O O O I I I I I I I I I I I I Function Line-In Left Channel. Line-In Right Channel. Center Channel Output. Low Frequency Enhanced Output. Line Out (Front) Left Channel. Line Out (Front) Right Channel. Monaural Output to Telephone Subsystem Speakerphone. Surround Front Headphone Left Channel Output. Surround Front Headphone Right Channel Output. Voltage Reference Filter. Voltage Reference Output 5 mA Drive (intended for MIC bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. Digital VDD 3.3 V. Digital GND. Digital GND. Digital VDD 3.3 V. Analog VDD 5.0 V. Analog GND. Analog GND. Analog VDD 5.0 V. Analog VDD 5.0 V. Analog GND. Analog VDD 5.0 V. Analog GND. No Connect. No Connect.
Rev. A | Page 10 of 32
AD1888
Table 6. Indexed Control Registers
Reg 00h 02h 04h 06h 0Ch 0Eh 10h 12h 16h 18h 1Ah 1Ch 20h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 36h 38h 3Ah 72h 74h 76h Name Reset Master Volume Headphone Volume Mono Volume Phone Volume MIC Volume Line-In Volume CD Volume AUX Volume PCM Out Volume Record Select Record Gain GeneralPurpose Audio Int. and Paging Power-Down Ctrl/Stat Ext'd Audio ID Ext'd Audio Stat/Ctrl PCM Front DAC Rate PCM Surr DAC Rate PCM C/LFE DAC Rate PCM L/R ADC Rate Center/LFE Volume Surround Volume SPDIF Control JACK SENSE Serial Configuration Misc Control Bits Vendor ID1 Vendor ID2 D15 X MM HPM MVM PHM MCM LVM CVM AVM OM X IM X I4 EAPD ID1 VFORCE SRF15 SRS15 SRCL15 SRA15 LM MUTE_L V JS SPRD SLOT 16 DACZ D14 SE4 X X X X X X X X X X X X X PR6 ID0 X SRF14 SRS14 SRCL14 SRA14 X X X JS1 DMX REGM2 AC97NC D13 SE3 LMV5 LHV5 X X X X X X X X X X X PR5 X PRK SRF13 SRS13 SRCL13 SRA13 LFE5 LSR5 SPSR1 JS0 DMX REGM1 MSPLT D12 SE2 LMV4 LHV4 X X X LLV4 LCV4 LAV4 LOV4 X X X X PR4 X PRJ SRF12 SRS12 SRCL12 SRA13 LFE4 LSR4 SPSR0 JS MT2 REGM0 LODIS D11 SE1 LMV3 LHV3 X X X LLV3 LCV3 LAV3 LOV3 X LIM3 DRSS1 I0 PR3 REV1 PRI SRF11 SRS11 SRCL11 SRA11 LFE3 LSR3 L JS MT1 REGM3 CLDIS D10 SE0 LMV2 LHV2 X X X LLV2 LCV2 LAV2 LOV2 LS2 LIM2 DRSS0 X PR2 REV0 SPCV SRF10 SRS10 SRCL10 SRA10 LFE2 LSR2 CC6 JS MT0 DRF HPSEL D9 ID9 LMV1 LHV1 X X X LLV1 LCV1 LAV1 LOV1 LS1 LIM1 X X PR1 AMAP X SRF9 SRS9 SRCL9 SRA9 LFE1 LSR1 CC5 X X DMIX1 D8 ID8 LMV0 LHV0 X X X LLV0 LCV0 LAV0 LOV0 LS0 LIM0 MS X PR0 LDAC ELDAC SRF8 SRS8 SRCL8 SRA8 LFE0 LSR0 CC4 X CHEN DMIX0 D7 ID7 MMRM 1 HPRM X X X LVRM
1 1
D6 ID6 X X X X M20 X X X X X
1
D5 ID5 RMV5 RHV5 MV5 X X X X X X X X X X X DSA1 SPSA1 SRF5 SRS5 SRCL5 SRA5 CNT5 RSR5 CC1 JS1 MD LBKS0 LOSEL
D4 ID4 RMV4 RHV4 MV4 PHV4 MCV4 RLV4 RCV4 RAV4 ROV4 X X X X X DSA0 SPSA0 SRF4 SRS4 SRCL4 SRA4 CNT4 RSR4 CC0 JS0 MD INTS SRU
D3 ID3 RMV3 RHV3 MV2 PHV3 MCV3 RLV3 RCV3 RAV3 ROV3 X RIM3 X PG3 REF X X SRF3 SRS3 SRCL3 SRA3 CNT3 RSR3 PRE JS1 ST X VREFH
D2 ID2 RMV2 RHV2 MV2 PHV2 MCV2 RLV2 RCV2 RAV2 ROV2 RS2 RIM2 X PG2 ANL SPDIF ESPDIF SRF2 SRS2 SRCL2 SRA2 CNT2 RSR2 COPY JS0 ST SPAL VREFD
D1 ID1 RMV1 RHV1 MV1 PHV1 MCV1 RLV1 RCV1 RAV1 ROV1 RS1 RIM1 X PG1 DAC DRA EDRA SRF1 SRS1 SRCL1 SRA1 CNT1 RSR1 /AUD JS1 INT SPDZ MBG1
D0 ID0 RMV0 RHV0 MV0 PHV0 MCV0 RLV0 RCV0 RAV0 ROV0 RS0 RIM0 X PG0 ADC VRA EVRA SRF0 SRS0 SRCL0 SRA0 CNT0 RSR0 PRO JS0 INT SPLNK MBG0
Default 0090h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 0000h 8000h 0000h xxxxh NA x3C7h 0xx0h BB80h BB80h BB80h BB80h 8080h 8080h 2000h 0000h 1001h 0000h
CDRM
1
AVRM1 OMRM1 X IMRM LPBK X X SDAC ESDAC SRF7 SRS7 SRCL7 SRA7 CM MUTE_R CC3 JS1 TMR X SPRD
X X X X CDAC ECDAC SRF6 SRS6 SRCL6 SRA6 X X CC2 JS0 TMR LBKS1 X
7Ch 7Eh
F7 T7
F6 T6
F5 T5
F4 T4
F3 T3
F2 T2
F1 T1
F0 T0
S7 REV7
S6 REV6
S5 REV5
S4 REV4
S3 REV3
S2 REV2
S1 REV1
S0 REV0
4144h 5368h
1
For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written to. Zeros should be written to reserved bits.
Rev. A | Page 11 of 32
AD1888
Table 7. Reset Register (Index 00h)
Reg No. 00h Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0090h
All registers not shown and bits containing an X are assumed to be reserved. Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following:
Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated Mic PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1888 0 0 0 0 1 0 0 1 0 0
SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.)
Table 8. Master Volume Register (Index 02h)
Reg No. 02h Name Master Volume D15 MM D14 X D13 1 LMV5 D12 LMV4 D11 LMV3 D10 LMV2 D9 LMV1 D8 LMV0 D7 MMRM 2 D6 X D51 RMV5 D4 RMV4 D3 RMV3 D2 RMV2 D1 RMV1 D0 RMV0 Default 8000h
1
Refer to Table 10 for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1. 2 For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: For AC97NC = 0, the register controls the Line_out output Attenuators only. For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.
RMV[5:0] MMRM LMV[5:0] MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM bit. Otherwise this bit will always read 0 and will have no effect when set to 1. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1.
Rev. A | Page 12 of 32
AD1888
Table 9. Headphones Volume Register (Index 04h)
Reg No. 04h Name Headphone Volume D15 HPM D14 X D13 LHV5 D12 LHV4 D11 LHV3 D10 LHV2 D9 LHV1 D8 LHV0 D7 HPRM1 D6 X D5 RHV5 D4 RHV4 D3 RHV3 D2 RHV2 D1 RHV1 D0 RHV0 Default 8000h
Table 10. Volume Settings for Master and Headphone
Reg. 76h MSPLTT 1 0 0 0 0 0 1 1 1
1
D15 0 0 0 0 1 0 1 1
WRITE 00 0000 00 1111 01 1111 1x xxxx xx xxxx 1x xxxx xx xxxx xx xxxx
Control Bits Master Volume (02h) and Headphone Volume (04h) Left Channel Volume D[13:8] Right Channel Volume D[5:0] 1 READBACK Function D7 WRITE READBACK Function 00 0000 0 dB Gain x 00 0000 00 0000 0 dB Gain 00 1111 -22.5 dB Gain x 00 1111 00 1111 -22.5 dB Gain 01 1111 -46.5 dB Gain x 01 1111 01 1111 -46.5 dB Gain 01 1111 -46.5 dB Gain x 1x xxxx 01 1111 -46.5 dB Gain xx xxxx - dB Gain, Muted x xx xxxx xx xxxx - dB Gain, Muted 01 1111 -46.5 dB Gain 1 xx xxxx xx xxxx - dB Gain, only Right Muted xx xxxx - dB Gain, Left only Muted 0 xx xxxx xx xxxx -46.5 dB Gain xx xxxx - dB Gain, Left Muted 1 xx xxxx xx xxxx - dB Gain, Right Muted
For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. x in the above table is don't care.
Table 11. Mono Volume Register (Index 06h)
Reg No. 06h
1
Name Mono Volume
D15 MVM
D14 X
D13 X
D12 X
D11 X
D10 X
D9 X
D8 X
D7 X
D6 X
D5 1 MV5
D4 MV4
D3 MV3
D2 MV2
D1 MV1
D0 MV0
Default 8000h
Refer to Table 12 for examples. This register controls the Mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1. All registers not shown and bits containing an X are assumed to be reserved.
MV[5:0] MVM
Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Mono Volume Mute. When this bit is set to 1, the channel is muted.
Table 12. Volume Settings for Mono
D15 0 0 0 1 WRITE 0 0000 0 1111 1 1111 x xxxx Control Bits D[4:0] for Mono (06h) READBACK 0 0000 0 1111 1 1111 x xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain - dB Gain, Muted
x in the above table is a wild card and has no effect on the value.
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Table 13. Phone_in Volume Register (Index 0Ch)
Reg No. 0Ch Name Phone_in Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PHV4 D3 PHV3 D2 PHV2 D1 PHV1 D0 PHV0 Default 8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 15 for examples.
PHV[4:0] PHM
Phone Volume. Allows setting the Phone Volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. Phone Mute. When this bit is set to 1, the Phone channel is muted.
Table 14. MIC Volume Register (Index 0Eh)
Reg No. 0Eh Name MIC Volume D15 MCM D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 M20 D5 X D4 MCV4 D3 MCV3 D2 MCV2 D1 MCV1 D0 MCV0 Default 8008h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 15 for examples.
MCV[4:0] M20
MCM
MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with mute enabled. MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB; however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 dB or 30 dB, if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1) MIC Mute. When this bit is set to 1, the channel is muted.
Table 15. Volume Settings for Phone and MIC
Control Bits D[4:0] Phone (0Ch) and MIC (0Eh) READBACK 0 0000 0 1000 1 1111 x xxxx
D15 0 0 0 1
WRITE 0 0000 0 1000 1 1111 x xxxx
Function 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted
x in the above table is a wild card, and has no effect on the value.
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Table 16. Line-In Volume Register (Index 10h)
Reg No. 10h Name Line-In Volume D15 LVM D14 X D13 X D12 LLV4 D11 LLV3 D10 LLV2 D9 LLV1 D8 LLV0 D7 LVRM 1 D6 X D5 X D4 RLV4 D3 RLV3 D2 RLV2 D1 RLV1 D0 RLV0 Default 8808h
1
For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 20 for examples.
RLV[4:0] LVRM LLV[4:0] LVM
Right Line-In Volume. Allows setting the Line-In Right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.d dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the LIM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Line-In Volume. Allows setting the Line-In left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line-In Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will only affect the left channel.
Table 17. CD Volume Register (Index 12h)
Reg No. 12h Name CD Volume D15 CVM D14 X D13 X D12 LCV4 D11 LCV3 D10 LCV2 D9 LCV1 D8 LCV0 D7 CDRM 1 D6 X D5 X D4 RCV4 D3 RCV3 D2 RCV2 D1 RCV1 D0 RCV0 Default 8808h
1
For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 20 or examples.
RCV[4:0] CDRM LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the Right channel separately from the CVM bit. Otherwise this bit will always read 0 and will have no effect when set to 1. Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -24.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table 18. AUX Volume Register (Index 16h)
Reg No. 16h Name AUX Volume D15 AVM D14 X D13 X D12 LAV4 D11 LAV3 D10 LAV2 D9 LAV1 D8 LAV0 D7 AVRM 1 D6 X D5 X D4 RAV4 D3 RAV3 D2 RAV2 D1 RAV1 D0 RAV0 Default 8808h
1
For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 20 for examples.
RAV[4:0] AVRM LAV[4:0] AVM
Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
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Table 19. PCM-Out Volume Register (Index 18h)
Reg No. 18h Name PCM Out Volume D15 OM D14 X D13 X D12 LOV4 D11 LOV3 D10 LOV2 D9 LOV1 D8 LOV0 D7 OMRM 1 D6 X D5 X D4 ROV4 D3 ROV3 D2 ROV2 D1 ROV1 D0 ROV0 Default 8808h
1
For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 20 for examples. Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality: For AC97NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators. For AC97NC = 1, the register controls the PCM Out Volume only.
ROV[4:0] OMRM LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table 20. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Reg. 76h MSPLTT 1 0 0 0 0 1 1 1
1
D15 0 0 0 1 0 1 1
WRITE 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx
Control Bits Line-In (10h), CD (12h), AUX (16h) and PCM-Out (18h) Left Channel Volume D[12:8] Right Channel Volume D[4:0] READBACK Function D71 WRITE READBACK Function 0 0000 12 dB Gain x 0 0000 0 0000 12 dB Gain 0 1000 0 dB Gain x 0 1000 0 1000 0 dB Gain 1 1111 -34.5 dB Gain x 1 1111 1 1111 -34.5 dB Gain x xxxx - dB Gain, Muted x x xxxx x xxxx - dB Gain, Muted 1 1111 -34.5 dB Gain 1 x xxxx x xxxx - dB Gain, Right Only Muted x xxxx - dB Gain, Left Only Muted 0 1 1111 1 1111 -34.5 dB Gain x xxxx - dB Gain, Left Muted 1 x xxxx x xxxx - dB Gain, Right Muted
For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, RM Bit has no effect. x in the above table is don't care.
Table 21. Record Select Control Register (Index 1Ah)
Reg No. 1Ah Name Record Select D15 X D14 X D13 X D12 X D11 X D10 LS2 D9 LS1 D8 LS0 D7 X D6 X D5 X D4 X D3 X D2 RS2 D1 RS1 D0 RS0 Default 0000h
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 22 for examples. Used to select the record source independently for the right and left channels. For MIC recording, see MS bit (Register 20h) for MIC1 and MIC2 input selection.
RS [2:0] LS [2:0]
Right Record Select Left Record Select
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Table 22. Settings for Record Select Control
LS [10:8] 000 001 010 011 100 101 110 111 Left Record Source MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN RS [2:0] 000 001 010 011 100 101 110 111 Right Record Source MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN
Table 23. Record Gain Register (Index 1Ch)
Reg No. 1Ch Name Record Gain D15 IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 LIM1 D8 LIM0 D7 IMRM 1 D6 X D5 X D4 X D3 RIM3 D2 RIM2 D1 RIM1 D0 RIM0 Default 8000h
1
For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 24 for examples.
RIM[3:0] IMRM LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Input Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
Table 24. Settings for Record Gain Register
Reg. 76h MSPLTT 1 0 0 0 1 1 1
1
Control Bits Record Gain (1Ch) D15 0 0 1 0 1 1 Left Channel Input Mixer D[11:8] WRITE READBACK Function 1111 1111 22.5 dB Gain 0000 0000 0 dB Gain xxxx xxxx - dB Gain, Muted 1111 1111 22.5 dB Gain xxxx xxxx - dB Gain, Left Only Muted xxxx xxxx - dB Gain, Left Muted D71 x x x 1 0 1 WRITE 1111 0000 xxxx xxxx 1111 xxxx Right Channel Input Mixer D[3:0] READBACK Function 1111 22.5 dB Gain 0000 0 dB Gain xxxx - dB Gain, Muted xxxx - dB Gain, Right Only Muted 1111 22.5 dB Gain xxxx - dB Gain, Right Muted
For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect.
x is don't care.
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AD1888
Table 25. General-Purpose Register (Index 20h)
Reg No. 20h Name GeneralPurpose D15 X D14 X D13 X D12 X D11 DRSS1 D10 DRSS0 D9 X D8 MS D7 LPBK D6 X D5 X D4 X D3 X D2 X D1 X D0 X Default 0000h
This register should be read before writing to generate a mask only for the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed to be reserved.
LPBK
MS
DRSS [1:0]
Loopback Control. This bit enables the digital internal loopback from the ADC to the front DAC. This feature is normally used for test and troubleshooting. 0 = No Loopback (Default) 1 = Loopback PCM digital data from ADC output to DAC See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center/LFE DACs. MIC Select. Selects Mono MIC input. 0 = Select MIC1, from rear panel MIC jack 1 = Select MIC2, from front panel MIC jack Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R (n + 1) data are by default provided in output slots 10 and 11. 00: PCM L, R n + 1 Data is on Slots 10, 11 (reset default) 01: PCM L, R n + 1 Data is on Slots 7, 8 10: Reserved 11: Reserved
Table 26. Audio Interrupt and Paging Mechanism Register (Index 24h)
Reg No. 24h Name Audio Interrupt and Paging D15 I4 D14 X D13 X D12 X D11 I0 D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 PG3 D2 PG2 D1 PG1 D0 PG0 Default xxxxh
This register controls the audio interrupt and paging mechanism. All registers not shown and bits containing an X are assumed to be reserved.
PG[3:0] I0
I4
Page Selector (Read Only). This register is used to describe page selector capability for extended features. Reading these bits returns 0h, which describes page selection as vendor specific only. INTERRUPT ENABLE (R/W). This enables interrupt generation. 0 = Interrupt Generation is Masked (Default) 1 = Interrupt Generation is Unmasked The S/W should not unmask the interrupt unless ensured by the AC '97 controller that no conflict is possible with modem slot 12 GPI functionality. AC '97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, S/W could poll the interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an interrupting event has occurred. INTERRUPT STATUS (R/W). This bit provides interrupt status and clear capability. 0 = Interrupt is Clear 1 = Interrupt was Generated Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the ac link will follow this bit change when interrupt enable (I0) is unmasked.
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Table 27. Power-Down Control/Status Register (Index 26h)
Reg No. 26h Name Power-Down Control/Status D15 EAPD D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 X D6 X D5 X D4 X D3 REF D2 ANL D1 DAC D0 ADC Default NA
The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1888 subsections. If the bit is a 1, then that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved.
ADC DAC ANL REF PR[6:0]
EAPD
ADC Sections Ready to Transmit Data DAC Sections Ready to Transmit Data Analog Amplifiers, Attenuators, and Mixers Ready Voltage References, VREF and VREFOUT, up to Nominal Level Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. External Audio Power-Down Control. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset defaults). EAPD = 1 sets the EAPD pin high, shutting off the external power amplifier.
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PR0 = 1 PR1 = 1 PR2 = 1 PR4 = 1
NORMAL
ADCs OFF PR0
DACs OFF PR1
ANALOG OFF PR2 OR PR3
DIGITAL I/F OFF PR4
SHUT OFF AC-LINK
PR0 = 0 AND ADC = 1
PR1 = 0 AND DAC = 1
PR2 = 0 AND ANL = 1
WARM RESET
READY = 1 DEFAULT
Figure 10. One Example of AC '97 Power-Down/Power-Up Flow
Table 28. Extended Audio ID Register (Index 28h)
Reg No. 28h Name Ext'd Audio ID D15 ID1 D14 ID0 D13 X D12 X D11 REV1 D10 REV0 D9 AMAP D8 LDAC D7 SDAC D6 CDAC D5 DSA1 D4 DSA0 D3 X D2 SPDIF D1 DRA D0 VRA Default x3C7h
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one or more of the extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved.
VRA DRA SPDIF
DSA[1,0]
CDAC SDAC LDAC AMAP REV[1,0] ID[1:0]
Variable Rate PCM Audio Support (Read Only). This bit returns a 1 when read to indicate that the Variable Rate PCM Audio is supported. Double Rate Audio (Read Only). This bit returns a 1 when read to indicate that the optional Double Rate RCM Audio is supported for PCM L and PCM R. SPDIF Support (Read Only). This bit returns a 1 when read to indicate that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DAC Slot Assignments (Read/Write) (Reset Default = 00) 00 DACs 1, 2 = 3 and 4 DACs 3, 4 = 7 and 8 DACs 5, 6 = 6 and 9 01 DACs 1, 2 = 7 and 8 DACs 3, 4 = 6 and 9 DACs 5, 6 = disabled 10 DACs 1, 2 = 6 and 9 DACs 3, 4 = disabled DACs 5, 6 = disabled 11 Reserved PCM CENTER DAC Support (Read Only). This bit returns a 1 when read to indicate that PCM center DAC is supported. PCM Surround DAC Support (Read Only). This bit returns a 1 when read to indicate that PCM surround left and right DACs are supported. PCM LFE DAC Support (Read Only), This bit returns a 1 when read to indicate that PCM LFE DAC is supported. Slot DAC Mappings Based on Codec ID (Read Only). This bit returns a 1 when read to indicate that slot/DAC mappings based on codec ID are supported. REV[1,0] = 01 indicates codec is AC '97 revision 2.2 compliant (Read Only). Indicates Codec Configuration (Read Only). 00 = Primary 01, 10, 11 = Secondary
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04294-010
COLD RESET
AD1888
Table 29. Extended Audio Status and Control Register (Index 2Ah)
Reg No. 2Ah Name Extended Audio Stat/Ctrl D15 VFORCE D14 X D13 PRK D12 PRJ D11 PRI D10 SPCV D9 X D8 ELDAC D7 ESDAC D6 ECDAC D5 SPSA1 D4 SPSA0 D3 X D2 ESPDIF D1 EDRA D0 EVRA
Default 0xx0h
The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers not shown and bits containing an X are assumed to be reserved.
EVRA
EDRA
ESPDIF
SPSA[1,0]
ECDAC ESDAC ELDAC SPCV
PRI PRJ PRK VFORCE
Variable Rate Audio (Read/Write). EVRA = 0, sets fixed sample rate audio at 48 kHz (Reset Default). EVRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). Double Rate Audio. EDRA = 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used in conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other DACs (surround, center, and LFE) are automatically powered down. Note that EDRA can be used without VRA; in that case, the converter rates are forced to 96 kHz if EDRA = 1. SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write). ESPDIF = 1 enables the SPDIF transmitter. ESPDIF = 0 disables the SPDIF transmitter (default). SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. See the following table. Center DAC Status (Read Only). ECDAC = 1 indicates the PCM center DAC is ready. Surround DAC status (Read Only). ESDAC = 1 indicates the PCM surround DACs are ready. LFE DAC status (Read Only). ELDAC = 1 indicates the PCM LFE DAC is ready. SPDIF Configuration Valid (Read Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported). Center DAC Power-Down (Read/Write). PRI = 1 turns off the PCM Center DAC. Surround DACs Power-Down (Read/Write). PRJ = 1 turns off the PCM surround DACs. LFE DAC Power-Down (Read/Write). PRK = 1 turns off the PCM LFE DAC. Validity Force Bit (Reset Default = 0). When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be con-trolled by the V bit (D15) in Register 3Ah (SPDIF control register). VFORCE = 0 and V = 0; the Validity Bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid. VFORCE = 1 and V = 0; the Validity Bit is forced low, indicating subframe data is valid. VFORCE = 1 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid.
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Table 30. AC '97 2.2 AMAP Compliant Default SPDIF Slot Assignments
Codec ID 00 00 00 01 01 10 10 11 Function 2-Ch Primary w/SPDIF 4-Ch Primary w/SPDIF 6-Ch Primary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 SPSA = 01 7 and 8 [default] 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 SPSA = 10 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9 SPSA = 11 10 and 11 10 and 11 10 and 11[default] 10 and 11[default] 10 and 11[default] 10 and 11[default]
Table 31. PCM Front DAC Rate Register (Index 2Ch)
Reg No. 2Ch Name PCM Front DAC Rate D15 SRF15 D14 SRF14 D13 SRF13 D12 SRF12 D11 SRF11 D10 SRF10 D9 SRF9 D8 SRF8 D7 SRF7 D6 SRF6 D5 SRF5 D4 SRF4 D3 SRF3 D2 SRF2 D1 SRF1 D0 SRF0 Default BB80h
This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz.
SRF[15:0]
Sample Rate The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz.
Table 32. PCM Surround DAC Rate Register (Index 2Eh)
Reg No. 2Eh Name PCM Surr DAC Rate D15 SRS15 D14 SRS14 D13 SRS13 D12 SRS12 D11 SRS11 D10 SRS10 D9 SRS9 D8 SRS8 D7 SRS7 D6 SRS6 D5 SRS5 D4 SRS4 D3 SRS3 D2 SRS2 D1 SRS1 D0 SRS0 Default BB80h
This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the surround DAC. This register's reset default is to be locked to the PCM front DAC sample rate register (2-Ch). To unlock this register, Bit SRU in Register 76h must be asserted.
SRF[15:0]
Sample Rate The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz.
Table 33. PCM LFE (and CENTER) DAC Rate Register (Index 30h)
Reg No. 30h Name PCM LFE/C DAC Rate D15 SRCL15 D14 SRCL14 D13 SRCL13 D12 SRCL12 D11 SRCL11 D10 SRCL10 D9 SRCL9 D8 SRCL8 D7 SRCL7 D6 SRCL6 D5 SRCL5 D4 SRCL4 D3 SRCL3 D2 SRCL2 D1 SRCL1 D0 SRCL0 Default BB80h
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the LFE DAC and Center DAC. This register's reset default is to be locked to the PCM Front DAC sample rate register (2-Ch) To unlock the register bit, SRU in Register 76h must be asserted.
SRF[15:0]
Sample Rate The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz.
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Table 34. PCM ADC Rate Register (Index 32h)
Reg No. 32h Name PCM L/R ADC Rate D15 SRA15 D14 SRA14 D13 SRA13 D12 SRA12 D11 SRA11 D10 SRA10 D9 SRA9 D8 SRA8 D7 SRA7 D6 SRA6 D5 SRA5 D4 SRA4 D3 SRA3 D2 SRA2 D1 SRA1 D0 SRA0 Default BB80h
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
SRF[15:0]
Sample Rate The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to EVRA, the sample rate is reset to 48 kHz.
Table 35. CENTER/LFE Volume Control Register (Index 36h)
Reg No. 36h Name Center/LFE Volume D15 LM D14 X D13 1 LFE5 D12 LFE4 D11 LFE3 D10 LFE2 D9 LFE1 D8 LFE0 D7 CM D6 X D51 CNT5 D4 CNT4 D3 CNT3 D2 CNT2 D1 CNT1 D0 CNT0 Default 8080h
Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bit is set to 1, its respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever this bit is set to 1. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table 36 for examples. This register controls the LFE output volume and mute bit. The volume registers contain five bits, generating 32 volume levels with 31 steps of 1.5 dB each. If MSPLT is not set, Bit D7 has no effect. Note that depending on the state of the AC97NC bit in Register 76h, this register operates as follows: For AC97NC = 0, the register controls the center and LFE output pin attenuators. Range is 0 dB to -46.5 dB. For AC97NC = 1, the register controls the center and LFE DAC gain/attenuators. Range is +12 dB to -34.5 dB.
1
CNT[5:0] CM LFE[5:0] LM
Center Volume Control Center Volume Mute. When this bit is set to 1, the channel is muted. LFE Volume Control LFE Volume Mute. When this bit is set to 1, the channel is muted.
Table 36. Settings for Center/LFE Register
Control Bits CENTER and LFE Volume (36h) D15/D7 0 0 0 0 1 CENTER D[5:0] and LFE D[13:8] WRITE READBACK 00 0000 00 0000 00 1111 00 1111 01 1111 01 1111 1x xxxx 01 1111 xx xxxx xx xxxx Function with AC97NC = 0 0 dB Gain -22 dB Gain -46.5 dB Gain -46.5 dB Gain Muted Function with AC97NC = 1 12 dB Gain -10.5 dB Gain -34.5 dB Gain Not Applicable Muted
Table 37. Surround Volume Control Register (Index 38h)
Reg No. 38h Name Surround Volume D15 MUTE_L D14 X D13 1 LSR5 D12 LSR4 D11 LSR3 D10 LSR2 D9 LSR1 D8 LSR0 D7 MUTE_R D6 X D51 RSR5 D4 RSR4 D3 RSR3 D2 RSR2 D1 RSR1 D0 RSR0 Default 8080h
1
Refer to Table 37 for examples. This register controls the surround volume controls for both stereo channels and mute bits. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 Bit is set to 1, its respective lower five volume bits are automatically set to 1 by the coded logic. On readback , all lower five bits will read 1s whenever these bits are set to 1.
Note that depending on the state of the AC97NC bit in Register 76h, this register operates as follows: For AC97NC = 0, the register controls the surround output pin attenuators. Range is 0 dB to -46.5 dB. For AC97NC = 1, the register controls the surround DAC gain/attenuators. Range is +12 dB to -34.5 dB.
RSR[5:0] MUTE_R LSR[5:0] MUTE_L
Right Surround Volume Control Right Surround Volume Mute. When this bit is set to 1, the right channel is muted. Left Surround Volume Control Left Surround Volume Mute. When this bit is set to 1, the left channel is muted.
Rev. A | Page 23 of 32
AD1888
Table 38. Settings for Surround Register
Control Bits Surround Volume (38h) Left Surround D[13:8] Right Surround D[5:0] WRITE READBACK 00 0000 00 0000 00 1111 00 1111 01 1111 01 1111 1x xxxx 01 1111 xx xxxx xx xxxx
D15/D7 0 0 0 0 1
Function with AC97NC = 0 0 dB Gain -22 dB Gain -46.5 dB Gain -46.5 dB Gain Muted
Function with AC97NC = 1 12 dB Gain -10.5 dB Gain -34.5 dB Gain Not Applicable Muted
Table 39. SPDIF Control Register (Index 3Ah)
Reg No. 3Ah Name SPDIF Control D15 V D14 X D13 SPSR1 D12 SPSR0 D11 L D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 PRE D2 COPY D1 /AUD D0 PRO Default 2000h
All registers not shown and bits containing an X are assumed to be reserved. Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF Bit in Register 2Ah is 0). This ensures that control and status information starts up correctly at the beginning of SPDIF transmission.
PRO /AUD COPY PRE CC[6-0] L SPSR[1,0]
V
Professional. 1 indicates professional use of channel status, 0 indicates consumer. Non-Audio. 1 indicates data is non PCM format, 0 indicates data is PCM. Copyright. 1 indicates copyright is asserted, 1 indicates copyright is not asserted. Pre-emphasis. 1 indicates filter pre-emphasis is 50 s/15 s, 0 indicates pre-emphasis is none. Category Code. Programmed according to IEC standards, or as appropriate. Generation Level. Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate: SPSR[1:0] = 00 Transmit Sample Rate = 44.1 kHz SPSR[1:0] = 01 Reserved SPSR[1:0] = 10 Transmit Sample Rate = 48 kHz (default) SPSR[1:0] = 11 Not supported. Validity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext'd Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid.
Rev. A | Page 24 of 32
AD1888
Table 40. Jack Sense/Audio Interrupt Status Register (Index 72h)
Reg No. 72h Name Jack Sense D15 JS1 SPRD D14 JS1 DMX D13 JS0 DMX D12 JS MT2 D11 JS MT1 D10 JS MT0 D9 X D8 X D7 JS1 TMR D6 JS0 TMR D5 JS1 MD D4 JS0 MD D3 JS1 ST D2 JS0 ST D1 JS1 INT D0 JS0 INT Default 0000h
All register bits are read/write except for JS0ST and JS1ST, which are read only.
JS0INT
JS1INT JS0ST JS1ST JS0MD
JS1MD
JS0TMR JS1TMR JSMT[2,0] JS0DMX
JS1DMX
JS1SPRD
Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR should clear this bit by writing a 0 to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also, note that the actual interrupt implementation is selected by the INTS bit (Register 76h). It is also possible to generate a software system interrupt by writing a 1 to this bit. Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT description for additional details. JS0 STATE. This bit always reports the logic state of the JS0 pin. JS1 STATE. This bit always reports the logic state of the JS1 pin. JS0 Mode. This bit selects the operation mode for the JS0 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS1 Mode. This bit selects the operation mode for the JS1 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 278 ms to be recognized. JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 278 ms to be recognized. JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table 41). JS0 Down Mix Control Enable. This bit enables JS0 to control the down-mix function. This function allows a digital mix of six channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_OUT or HP_OUT jacks. When this bit is set to 1, JS0 = 1 will activate the down-mix conversion. See the DMIX description in Register 76h. The DMIX bits select the down-mix implementation type and can also force the function to be activated. JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active (logic state 1). Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit's description in Register 76h for a better understanding of the spread function. JS Spread Control Enable. This bit enables 2-channel to 6-channel audio spread function when both Jack Senses are active (logic state 1). Note that the SPRD bit can also force the spread function without being gated by the Jack Senses. See this bit's description in Register 76h for a better understanding of the spread function.
Rev. A | Page 25 of 32
AD1888
Table 41. Jack Sense Mute Select (JSMT [2:0])
JS1 NA OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) OUT (0) OUT (0) IN (1) IN (1) NA NA NA JS0 NA OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) OUT (0) IN (1) NA NA NA JSMT2 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 JSMT1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 JSMT0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 HP OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ** ** ** LINE OUT ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE FMUTE ACTIVE ACTIVE ** ** ** C/LFE OUT ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE ACTIVE FMUTE FMUTE FMUTE FMUTE ACTIVE ACTIVE ** ** ** MONO OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE FMUTE ACTIVE FMUTE FMUTE FMUTE ** ** ** Notes JS0 and JS1 ignored. JS0 no mute action, JS1 mutes mono and enables LINE_OUT and C/LFE. Standard 6-channel config. JS0 = 0 and JS1 = 0 enables mono. JS1 = 1 enables front only JS0 = 1 enables all rear. 6-chan config with front jack wrapback. JS0 no mute action, JS1 mutes mono and enables LINE_OUT + HP_OUT + C/LFE. Standard 6-channel config. ** Reserved ** Reserved ** Reserved
FMUTE = Output is forced to mute independent of the respective Volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective Volume register setting. OUT = Nothing plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is 1 (via the codec JS internal pull-up).
Rev. A | Page 26 of 32
AD1888
Table 42. Serial Configuration Register (Index 74h)
Reg No. 74h Name Serial Config D15 SLOT16 D14 REGM2 D13 REGM1 D12 REGM0 D11 REGM3 D10 DRF D9 X D8 CHEN D7 X D6 LBKS1 D5 LBKS0 D4 INTS D3 X D2 SPAL D1 SPDZ D0 SPLNK Default 1001h
SPLNK
SPDZ
SPAL
INTS
LBKS[1:0]
CHEN
DRF
REGM3 REGM0 REGM1 REGM2 SLOT16
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the same data requests (reset default). SPDIF DACZ. 0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO underruns. SPDIF ADC Loop-Around. 0 = SPDIF transmitter is connected to the AC-Link stream (reset default). 1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link. Interrupt Mode Select. This bit selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (modem interrupt) (reset default). 1 = Slot 6 Valid Bit (MIC ADC interrupt). Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h) 00 = Loop-back through the front DACs (reset default). 01 = Loop-back through the surround DACs. 10 = Reserved 11 = Loop-back through the center and LFE DACs (center DAC loops back from the ADC left channel, the LFE DAC from the ADC right channel). Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin. DAC Request Force. This allows the AD1888 to synchronize DAC requests with the AD1981A/B. 0 = Normal DAC requesting sequence (reset default). 1 = Synchronize to AD1981A/B DAC requests. Slave 3 Codec Register Mask Master Codec Register Mask Slave 1 Codec Register Mask Slave 2 Codec Register Mask Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing.
Rev. A | Page 27 of 32
AD1888
Table 43. Miscellaneous Control Bit Register (Index 76h)
Reg No. 76h Name Misc Control Bits D15 DACZ D14 AC97NC D13 MSPLT D12 LODIS D11 CLDIS D10 HPSEL D9 DMIX1 D8 DMIX0 D7 SPRD D6 X D5 LOSEL D4 SRU D3 VREFH D2 VREFD D1 MBG1 D0 MBG0 Default 0000h
MBG[1:0]
VREFD
VREFH
SRU
LOSEL
SPRD
MIC Boost Gain Select Register. These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Both MIC1/MIC2 and MIC2 preamps will be set to the same selected gain. Note that this gain takes effect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise, the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default) 01 = 10 dB gain 10 = 30 dB gain 11 = reserved VREFOUT Disable. Disables VREFOUT, placing it into High-Z out mode. Note that this bit overrides the VREFH bit selection (see below). 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into High-Z out mode. VREFOUT High. Changes VREFOUT from 2.25 V to 3.70 V for PC2001 compliant MIC bias applications. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 3.70 V output. Sample Rate Unlock. Controls DAC sample rate locking. 0 = All DAC sample rates are locked to the front sample rate (reset default) 1 = DAC sample rates can be set independently for front, surround, and LFE. LINE_OUT Amplifiers Input Select. This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is to allow swapping of the front and surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit should normally be used in tandem with the HPSEL bit (see below). 0 = LINE_OUT amplifiers are driven by the mixer outputs (reset default). 1 = LINE_OUT amplifiers are driven by the surround DAC outputs. SPREAD Enable. This bit enables spreading of 2-channel media to all six output channels. This function is implemented in the analog section by using the output selector controls line for the center/LFE, surround, and Line_out output channels. Note that the Jack Sense pins can also be set up to control (gate) this function, depending on the JSSPRD bit (see Register 72h). 0 = No spreading occurs unless activated by the Jack Senses and JSSPRD bits (reset default). 1 = The SPRD selector drives the center and LFE outputs from the MONO_OUT, the HPSEL selector drives the SURR/HP_OUT outputs from the mixer outputs, and the LOSEL selector drives the LINE_OUT outputs also from the mixer outputs. Note that the SPRD bit overrides the current output selector control lines set up by bits LOSEL and HPSEL as follows: LOSEL = 0 and HPSEL = 1.
Rev. A | Page 28 of 32
AD1888
DMIX[1:0] Down Mix Mode Select. Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. Note that the Jack Sense pins can also be set up to control (gate) this function depending on the JS0DMX and JS1DMX Bits (see Register 72h). The upper bit allows forcing the down-mix function: DMIX[1] = 0, no down-mix unless activated by the Jack Sense and JSxDMX bits (default). DMIX[1] = 1, forces down-mix function. The lower bit selects the down-mix type: DMIX[0] = 0, selects 6-to-4 down-mix. The center and LFE channels are summed equally into the mixer left and right channels (default). DMIX[0] = 1, selects 6-to-2 down-mix. The surround left and right channels are summed into the mixer left and right channels. Default for DMIX[1:0] is 00. Headphone Amplifier Input Select. This bit allows the headphone power amps to be driven from the surround DACs or from the mixer outputs. There are two reasons for this: one is to allow 2-channel media to use the higher power headphone amplifiers available on the SURR/HP_OUT outputs; the other is to allow spreading of 2-channel media to the surround outputs. Together with the LOSEL bit (see above), this bit also provides for analog swapping of the mixer (front) and surround outputs. 0 = SURR_OUT/HP_OUToutputs are driven by the surround DACs (reset default). 1 = SURR_OUT/HP_OUToutputs are driven by the mixer outputs. Center and LFE Disable. Disables the center and LFE output pins, placing them into High-Z mode so that the assigned output audio jack(s) can be shared for MIC inputs or other functions. 0 = Center and LFE output pins have normal audio drive capability (reset default). 1 = Center and LFE output pins are placed into High-Z mode. Line_out Disable. Disables the Line_out pins (L/R), placing them into High-Z mode so that the assigned output audio jack can be shared for Line Input function. 0 = Line_out pins have normal audio drive capability (reset default). 1 = Line_out pins are placed into High-Z mode. Mute Split. Allows separate mute control bits for master, HP, Line_in, CD, PCM OUT, and record volume/gain control registers. 0 = Both left and right channel mutes are controlled by Bit D15 in the respective registers (reset default). 1 = Bit D15 affects only the left channel mute and Bit D7 affects only the right channel mute. AC '97 No Compatibility Mode. This bit allows the surround, center, and LFE volume control registers and output attenuators to operate in a more functional mode than defined by the AC97 2.2 spec. This is called ADI compatibility mode. In AC '97 compatibility mode, the DAC gain/attenuators for the surround, center, and LFE are controlled by Register 18h (PCM volume). The output pin attenuators for the surround are controlled by Register 38h, and the output pin attenuators for the center and LFE are controlled by Register 36h. In ADI compatibility mode, the Surround DAC gain/attenuators are controlled by Register 38h, and the Center/LFE DACs are controlled by Register 36h. The output pin attenuators for Center/LFE are controlled by Register 02h (Master Volume), and the output pin attenuators for Surround are controlled by Register 04h. 0 = AC97 compatibility mode (reset default). 1 = ADI compatibility mode. DAC Zero-Fill. Determines DAC data fill under starved condition. 0 = DAC data is repeated when DACs are starved for data (reset default). 1 = DAC data is zero-filled when DACs are starved for data.
HPSEL
CLDIS
LODIS
MSPLT
AC97NC
DACZ
Rev. A | Page 29 of 32
AD1888
Table 44. Vendor ID Register (Index 7Ch-7Eh)
Reg No. 7Ch Name Vendor ID1 D15 F7 D14 F6 D13 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 Default 4144h
S[7:0] F[7:0]
This register is ASCII encoded to A. This register is ASCII encoded to D.
Reg No. 7Eh
Name Vendor ID2
D15 T7
D14 T6
D13 T5
D12 T4
D11 T3
D10 T2
D9 T1
D8 T0
D7 REV7
D6 REV6
D5 REV5
D4 REV4
D3 REV3
D2 REV2
D1 REV1
D0 REV0
Default 5368h
T[7:0] REV[7:0]
This register is ASCII encoded to S. This register is set to 68h identifying the AD1888.
Table 45. Codec ID and Clock Selection Table
XTL_IN GND GND GND XTAL into XTL_IN CLK INPUT CLK INPUT CLK INPUT ID1# 0 0 1 1 0 0 1 ID0# 0 1 0 1 0 1 X Codec ID SECONDARY, ID = 3 SECONDARY, ID = 2 SECONDARY, ID = 1 PRIMARY, ID = 0 PRIMARY, ID = 0 PRIMARY, ID = 0 RESERVED Codec Clocking Source 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 24.576 MHz Local XTAL or External CLK 14.3181 MHz (External into XTL_IN) 48.00 MHz (External into XTL_IN) RESERVED
Note that internally, the ID pins have weak pull-ups and are inverted.
Rev. A | Page 30 of 32
AD1888 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
48 1
PIN 1
9.00 BSC SQ
37 36
1.45 1.40 1.35
TOP VIEW
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
(PINS DOWN)
7.00 BSC SQ
0.15 0.05
12 13 24
25
SEATING PLANE
VIEW A
0.50 BSC LEAD PITCH
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
0.27 0.22 0.17
Figure 11. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 12. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD1888JST AD1888JST-REEL AD1888JSTZ 1 AD1888JSTZ-REEL1 AD1888JCP AD1888JCP-REEL AD1888JCPZ1 AD1888JCPZ-REEL1
1
Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
Package Description 48-Lead LQFP, Tray Version 48-Lead LQFP, Reel Version 48-Lead LQFP, Tray Version 48-Lead LQFP, Reel Version 48-Lead LFCSP_VQ, Tray Version 48-Lead LFCSP_VQ, Reel Version 48-Lead LFCSP_VQ, Tray Version 48-Lead LFCSP_VQ, Reel Version
Package Option ST-48 ST-48 ST-48 ST-48 CP-48-1 CP-48-1 CP-48-1 CP-48-1
Z = Pb-free part.
Rev. A | Page 31 of 32
AD1888 NOTES
(c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04294-0-8/05(A)
T T
Rev. A | Page 32 of 32

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